GAL20V8B-25LPNI
vs
GAL20V8B-25LPN
feature comparison
All Stats
Differences Only
Pbfree Code
Rohs Code
Part Life Cycle Code
Obsolete
Obsolete
Ihs Manufacturer
LATTICE SEMICONDUCTOR CORP
LATTICE SEMICONDUCTOR CORP
Part Package Code
DIP
DIP
Package Description
DIP-24
DIP-24
Pin Count
24
24
Reach Compliance Code
unknown
unknown
HTS Code
8542.39.00.01
8542.39.00.01
Samacsys Manufacturer
Lattice Semiconductor
Lattice Semiconductor
Architecture
PAL-TYPE
PAL-TYPE
Clock Frequency-Max
37 MHz
37 MHz
JESD-30 Code
R-PDIP-T24
R-PDIP-T24
JESD-609 Code
e3
e3
Length
31.75 mm
31.75 mm
Number of Dedicated Inputs
12
12
Number of I/O Lines
8
8
Number of Inputs
20
20
Number of Outputs
8
8
Number of Product Terms
64
64
Number of Terminals
24
24
Operating Temperature-Max
85 °C
75 °C
Operating Temperature-Min
-40 °C
Organization
12 DEDICATED INPUTS, 8 I/O
12 DEDICATED INPUTS, 8 I/O
Output Function
MACROCELL
MACROCELL
Package Body Material
PLASTIC/EPOXY
PLASTIC/EPOXY
Package Code
DIP
DIP
Package Equivalence Code
DIP24,.3
DIP24,.3
Package Shape
RECTANGULAR
RECTANGULAR
Package Style
IN-LINE
IN-LINE
Peak Reflow Temperature (Cel)
260
260
Programmable Logic Type
EE PLD
EE PLD
Propagation Delay
25 ns
25 ns
Qualification Status
Not Qualified
Not Qualified
Seated Height-Max
5.334 mm
5.334 mm
Supply Voltage-Max
5.5 V
5.25 V
Supply Voltage-Min
4.5 V
4.75 V
Supply Voltage-Nom
5 V
5 V
Surface Mount
NO
NO
Technology
CMOS
CMOS
Temperature Grade
INDUSTRIAL
COMMERCIAL EXTENDED
Terminal Finish
MATTE TIN
MATTE TIN
Terminal Form
THROUGH-HOLE
THROUGH-HOLE
Terminal Pitch
2.54 mm
2.54 mm
Terminal Position
DUAL
DUAL
Width
7.62 mm
7.62 mm
Base Number Matches
1
1
Compare GAL20V8B-25LPNI with alternatives
Compare GAL20V8B-25LPN with alternatives