GAL16V8-25LJM vs GAL16V8D-25LPN feature comparison

GAL16V8-25LJM Texas Instruments

Buy Now Datasheet

GAL16V8D-25LPN Lattice Semiconductor Corporation

Buy Now Datasheet
Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer NATIONAL SEMICONDUCTOR CORP LATTICE SEMICONDUCTOR CORP
Package Description DIP, LEAD FREE, PLASTIC, DIP-20
Reach Compliance Code unknown unknown
ECCN Code 3A001.A.2.C EAR99
HTS Code 8542.39.00.01 8542.39.00.01
Additional Feature POWER-UP RESET; REGISTER PRELOAD
Clock Frequency-Max 28.5 MHz 37 MHz
JESD-30 Code R-GDIP-T20 R-PDIP-T20
Length 24.51 mm 26.162 mm
Number of Dedicated Inputs 8 8
Number of I/O Lines 8 8
Number of Terminals 20 20
Operating Temperature-Max 125 °C 70 °C
Operating Temperature-Min -55 °C
Organization 8 DEDICATED INPUTS, 8 I/O 8 DEDICATED INPUTS, 8 I/O
Output Function MACROCELL MACROCELL
Package Body Material CERAMIC, GLASS-SEALED PLASTIC/EPOXY
Package Code DIP DIP
Package Shape RECTANGULAR RECTANGULAR
Package Style IN-LINE IN-LINE
Programmable Logic Type EE PLD EE PLD
Propagation Delay 25 ns 25 ns
Qualification Status Not Qualified Not Qualified
Seated Height-Max 5.08 mm 5.334 mm
Supply Voltage-Max 5.5 V 5.25 V
Supply Voltage-Min 4.5 V 4.75 V
Supply Voltage-Nom 5 V 5 V
Surface Mount NO NO
Technology CMOS CMOS
Temperature Grade MILITARY COMMERCIAL
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Pitch 2.54 mm 2.54 mm
Terminal Position DUAL DUAL
Width 7.62 mm 7.62 mm
Base Number Matches 1 1
Pbfree Code Yes
Rohs Code Yes
Part Package Code DIP
Pin Count 20
Samacsys Manufacturer Lattice Semiconductor
Architecture PAL-TYPE
JESD-609 Code e3
Number of Inputs 18
Number of Outputs 8
Number of Product Terms 64
Package Equivalence Code DIP20,.3
Peak Reflow Temperature (Cel) 260
Terminal Finish MATTE TIN
Time@Peak Reflow Temperature-Max (s) 30

Compare GAL16V8-25LJM with alternatives

Compare GAL16V8D-25LPN with alternatives