EPM5130JC84 vs EPM5130GC100-1 feature comparison

EPM5130JC84 Cypress Semiconductor

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EPM5130GC100-1 Altera Corporation

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Part Life Cycle Code Obsolete Transferred
Ihs Manufacturer CYPRESS SEMICONDUCTOR CORP ALTERA CORP
Part Package Code QFJ PGA
Package Description WQCCJ, WPGA, PGA100M,13X13
Pin Count 84 100
Reach Compliance Code unknown unknown
HTS Code 8542.39.00.01 8542.39.00.01
Additional Feature 128 MACROCELLS; SHARED INPUT/CLOCK; SHARED PRODUCT TERMS 128 MACROCELLS; SHARED INPUT/CLOCK; SHARED PRODUCT TERMS
Clock Frequency-Max 33.3 MHz 50 MHz
JESD-30 Code S-CQCC-J84 S-CPGA-P100
Length 29.21 mm 33.528 mm
Number of Dedicated Inputs 19 19
Number of I/O Lines 48 64
Number of Terminals 84 100
Operating Temperature-Max 70 °C 70 °C
Operating Temperature-Min
Organization 19 DEDICATED INPUTS, 48 I/O 19 DEDICATED INPUTS, 64 I/O
Output Function MACROCELL MACROCELL
Package Body Material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
Package Code WQCCJ WPGA
Package Equivalence Code LDCC84,1.2SQ PGA100M,13X13
Package Shape SQUARE SQUARE
Package Style CHIP CARRIER, WINDOW GRID ARRAY, WINDOW
Programmable Logic Type UV PLD UV PLD
Propagation Delay 55 ns 40 ns
Qualification Status Not Qualified Not Qualified
Seated Height-Max 5.08 mm 4.96 mm
Supply Voltage-Max 5.25 V 5.25 V
Supply Voltage-Min 4.75 V 4.75 V
Supply Voltage-Nom 5 V 5 V
Surface Mount YES NO
Technology CMOS CMOS
Temperature Grade COMMERCIAL COMMERCIAL
Terminal Form J BEND PIN/PEG
Terminal Pitch 1.27 mm 2.54 mm
Terminal Position QUAD PERPENDICULAR
Width 29.21 mm 33.528 mm
Base Number Matches 2 2
Rohs Code No
In-System Programmable NO
JESD-609 Code e0
JTAG BST NO
Moisture Sensitivity Level 1
Number of Macro Cells 128
Peak Reflow Temperature (Cel) 220
Terminal Finish TIN LEAD

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