EPM5128GI68-1
vs
CY7C342B-30HC
feature comparison
All Stats
Differences Only
Part Life Cycle Code
Transferred
Obsolete
Ihs Manufacturer
ALTERA CORP
CYPRESS SEMICONDUCTOR CORP
Part Package Code
PGA
LCC
Package Description
WPGA,
WQCCJ, LDCC68,1.0SQ
Pin Count
68
68
Reach Compliance Code
unknown
not_compliant
HTS Code
8542.39.00.01
8542.39.00.01
Additional Feature
128 MACROCELLS; 8 LABS
LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Clock Frequency-Max
62.5 MHz
27.7 MHz
JESD-30 Code
S-CPGA-P68
S-CQCC-J68
Length
27.94 mm
24.13 mm
Number of Dedicated Inputs
7
7
Number of I/O Lines
52
52
Number of Terminals
68
68
Operating Temperature-Max
85 °C
70 °C
Operating Temperature-Min
-40 °C
Organization
7 DEDICATED INPUTS, 52 I/O
7 DEDICATED INPUTS, 52 I/O
Output Function
MACROCELL
MACROCELL
Package Body Material
CERAMIC, METAL-SEALED COFIRED
CERAMIC, METAL-SEALED COFIRED
Package Code
WPGA
WQCCJ
Package Equivalence Code
PGA68,11X11
LDCC68,1.0SQ
Package Shape
SQUARE
SQUARE
Package Style
GRID ARRAY, WINDOW
CHIP CARRIER, WINDOW
Programmable Logic Type
UV PLD
UV PLD
Propagation Delay
40 ns
60 ns
Qualification Status
Not Qualified
Not Qualified
Seated Height-Max
4.96 mm
5.08 mm
Supply Voltage-Max
5.5 V
5.25 V
Supply Voltage-Min
4.5 V
4.75 V
Supply Voltage-Nom
5 V
5 V
Surface Mount
NO
YES
Technology
CMOS
CMOS
Temperature Grade
INDUSTRIAL
COMMERCIAL
Terminal Form
PIN/PEG
J BEND
Terminal Pitch
2.54 mm
1.27 mm
Terminal Position
PERPENDICULAR
QUAD
Width
27.94 mm
24.13 mm
Base Number Matches
2
1
Rohs Code
In-System Programmable
NO
JESD-609 Code
e0
JTAG BST
NO
Number of Macro Cells
128
Terminal Finish
TIN LEAD
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