EP910IDI-25 vs PPLD910-15 feature comparison

EP910IDI-25 Altera Corporation

Buy Now Datasheet

PPLD910-15 Intel Corporation

Buy Now Datasheet
Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer ALTERA CORP INTEL CORP
Part Package Code DIP DIP
Package Description WDIP, DIP, DIP40,.6
Pin Count 40 40
Reach Compliance Code unknown compliant
HTS Code 8542.39.00.01 8542.39.00.01
Additional Feature MACROCELLS INTERCONNECTED BY GLOBAL BUS; 24 MACROCELLS; 2 EXTERNAL CLOCKS PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
Clock Frequency-Max 40 MHz 45.4 MHz
JESD-30 Code R-GDIP-T40 R-PDIP-T40
Length 52.07 mm 52.26 mm
Number of Dedicated Inputs 12 12
Number of I/O Lines 24 24
Number of Terminals 40 40
Operating Temperature-Max 85 °C 70 °C
Operating Temperature-Min -40 °C
Organization 12 DEDICATED INPUTS, 24 I/O 12 DEDICATED INPUTS, 24 I/O
Output Function MACROCELL MACROCELL
Package Body Material CERAMIC, GLASS-SEALED PLASTIC/EPOXY
Package Code WDIP DIP
Package Equivalence Code DIP40,.6 DIP40,.6
Package Shape RECTANGULAR RECTANGULAR
Package Style IN-LINE, WINDOW IN-LINE
Programmable Logic Type UV PLD OT PLD
Propagation Delay 28 ns 18 ns
Qualification Status Not Qualified Not Qualified
Seated Height-Max 5.75 mm 5.08 mm
Supply Voltage-Max 5.5 V 5.25 V
Supply Voltage-Min 4.5 V 4.75 V
Supply Voltage-Nom 5 V 5 V
Surface Mount NO NO
Technology CMOS CMOS
Temperature Grade INDUSTRIAL COMMERCIAL
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Pitch 2.54 mm 2.54 mm
Terminal Position DUAL DUAL
Width 15.24 mm 15.24 mm
Base Number Matches 1 1
Rohs Code No
Architecture PAL-TYPE
JESD-609 Code e0
Number of Inputs 36
Number of Outputs 24
Number of Product Terms 240
Terminal Finish TIN LEAD

Compare EP910IDI-25 with alternatives

Compare PPLD910-15 with alternatives