EP900DC-3
vs
EP910PC-35
feature comparison
All Stats
Differences Only
Pbfree Code
Rohs Code
Part Life Cycle Code
Obsolete
Active
Ihs Manufacturer
ALTERA CORP
ROCHESTER ELECTRONICS LLC
Part Package Code
DIP
Package Description
WDIP, DIP40,.6
DIP,
Pin Count
40
Reach Compliance Code
compliant
unknown
HTS Code
8542.39.00.01
Additional Feature
24 MACROCELLS
Architecture
PAL-TYPE
Clock Frequency-Max
23.8 MHz
37 MHz
JESD-30 Code
R-GDIP-T40
R-PDIP-T40
JESD-609 Code
e0
e0
Length
52.07 mm
Number of Dedicated Inputs
12
12
Number of I/O Lines
24
24
Number of Inputs
36
Number of Outputs
24
Number of Product Terms
240
Number of Terminals
40
40
Operating Temperature-Max
70 °C
70 °C
Operating Temperature-Min
Organization
12 DEDICATED INPUTS, 24 I/O
12 DEDICATED INPUTS, 24 I/O
Output Function
MACROCELL
MACROCELL
Package Body Material
CERAMIC, GLASS-SEALED
PLASTIC/EPOXY
Package Code
WDIP
DIP
Package Equivalence Code
DIP40,.6
Package Shape
RECTANGULAR
RECTANGULAR
Package Style
IN-LINE, WINDOW
IN-LINE
Peak Reflow Temperature (Cel)
220
NOT SPECIFIED
Programmable Logic Type
UV PLD
OT PLD
Propagation Delay
50 ns
35 ns
Qualification Status
Not Qualified
COMMERCIAL
Seated Height-Max
5.715 mm
Supply Voltage-Max
5.25 V
5.25 V
Supply Voltage-Min
4.75 V
4.75 V
Supply Voltage-Nom
5 V
5 V
Surface Mount
NO
NO
Technology
CMOS
CMOS
Temperature Grade
COMMERCIAL
COMMERCIAL
Terminal Finish
TIN LEAD
TIN LEAD
Terminal Form
THROUGH-HOLE
THROUGH-HOLE
Terminal Pitch
2.54 mm
Terminal Position
DUAL
DUAL
Width
15.24 mm
Base Number Matches
1
3
Time@Peak Reflow Temperature-Max (s)
NOT SPECIFIED
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