DSPIC33FJ32MC202T-H/SP
vs
DSPIC33FJ64MC506ATH/MR
feature comparison
| Pbfree Code |
Yes
|
|
| Rohs Code |
Yes
|
Yes
|
| Part Life Cycle Code |
Active
|
Active
|
| Ihs Manufacturer |
MICROCHIP TECHNOLOGY INC
|
MICROCHIP TECHNOLOGY INC
|
| Part Package Code |
DIP
|
QFN
|
| Package Description |
DIP,
|
9 X 9 MM, 0.90 MM HEIGHT, 0.50 MM, LEAD FREE, PLASTIC, QFN-64
|
| Pin Count |
28
|
64
|
| Reach Compliance Code |
compliant
|
compliant
|
| ECCN Code |
3A991.A.2
|
3A991.A.2
|
| HTS Code |
8542.31.00.01
|
8542.31.00.01
|
| Address Bus Width |
|
|
| Bit Size |
16
|
16
|
| Clock Frequency-Max |
40 MHz
|
40 MHz
|
| External Data Bus Width |
|
|
| JESD-30 Code |
R-PDIP-T28
|
S-PQCC-N64
|
| JESD-609 Code |
e3
|
e3
|
| Length |
34.671 mm
|
9 mm
|
| Number of Terminals |
28
|
64
|
| Operating Temperature-Max |
85 °C
|
150 °C
|
| Operating Temperature-Min |
-40 °C
|
-40 °C
|
| Package Body Material |
PLASTIC/EPOXY
|
PLASTIC/EPOXY
|
| Package Code |
DIP
|
HVQCCN
|
| Package Shape |
RECTANGULAR
|
SQUARE
|
| Package Style |
IN-LINE
|
CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
|
| Peak Reflow Temperature (Cel) |
NOT SPECIFIED
|
|
| Qualification Status |
Not Qualified
|
Not Qualified
|
| ROM Programmability |
FLASH
|
FLASH
|
| Seated Height-Max |
5.08 mm
|
1 mm
|
| Supply Voltage-Max |
3.6 V
|
3.6 V
|
| Supply Voltage-Min |
3 V
|
3 V
|
| Supply Voltage-Nom |
3.3 V
|
3.3 V
|
| Surface Mount |
NO
|
YES
|
| Technology |
CMOS
|
CMOS
|
| Temperature Grade |
INDUSTRIAL
|
AUTOMOTIVE
|
| Terminal Finish |
Matte Tin (Sn)
|
Matte Tin (Sn)
|
| Terminal Form |
THROUGH-HOLE
|
NO LEAD
|
| Terminal Pitch |
2.54 mm
|
0.5 mm
|
| Terminal Position |
DUAL
|
QUAD
|
| Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED
|
|
| Width |
7.62 mm
|
9 mm
|
| uPs/uCs/Peripheral ICs Type |
DIGITAL SIGNAL PROCESSOR, CONTROLLER
|
DIGITAL SIGNAL PROCESSOR, CONTROLLER
|
| Base Number Matches |
1
|
1
|
| Has ADC |
|
YES
|
| Barrel Shifter |
|
YES
|
| Boundary Scan |
|
YES
|
| DAC Channels |
|
NO
|
| DMA Channels |
|
YES
|
| Format |
|
FIXED POINT
|
| Integrated Cache |
|
NO
|
| Internal Bus Architecture |
|
MULTIPLE
|
| Low Power Mode |
|
YES
|
| Number of DMA Channels |
|
8
|
| Number of External Interrupts |
|
5
|
| Number of I/O Lines |
|
53
|
| Number of Serial I/Os |
|
4
|
| Number of Timers |
|
9
|
| On Chip Data RAM Width |
|
8
|
| On Chip Program ROM Width |
|
8
|
| PWM Channels |
|
YES
|
| Package Equivalence Code |
|
LCC64,.35SQ,20
|
| RAM (words) |
|
8192
|
| Screening Level |
|
AEC-Q100; TS 16949
|
| Speed |
|
20 MHz
|
| Supply Current-Max |
|
90 mA
|
|
|
|
Compare DSPIC33FJ32MC202T-H/SP with alternatives
Compare DSPIC33FJ64MC506ATH/MR with alternatives