DS2012R-65 vs CLS1-67204L-55 feature comparison

DS2012R-65 Dallas Semiconductor

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CLS1-67204L-55 Matra MHS

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Rohs Code No
Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer DALLAS SEMICONDUCTOR MATRA MHS
Reach Compliance Code unknown unknown
Access Time-Max 65 ns 55 ns
Additional Feature RETRANSMIT RETRANSMIT; 2V DATA RETENTION
Clock Frequency-Max (fCLK) 12.5 MHz
Cycle Time 80 ns 70 ns
JESD-30 Code S-PQCC-J32 R-PQCC-J32
JESD-609 Code e0
Memory Density 36864 bit 36864 bit
Memory IC Type OTHER FIFO OTHER FIFO
Memory Width 9 9
Number of Functions 1 1
Number of Terminals 32 32
Number of Words 4096 words 4096 words
Number of Words Code 4000 4000
Operating Mode ASYNCHRONOUS ASYNCHRONOUS
Operating Temperature-Max 70 °C 70 °C
Operating Temperature-Min
Organization 4KX9 4KX9
Output Characteristics 3-STATE 3-STATE
Output Enable NO NO
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Code QCCJ
Package Equivalence Code LDCC32,.5X.6
Package Shape SQUARE RECTANGULAR
Package Style CHIP CARRIER CHIP CARRIER
Parallel/Serial PARALLEL PARALLEL
Qualification Status Not Qualified Not Qualified
Standby Current-Max 0.002 A
Supply Current-Max 0.12 mA 0.065 mA
Supply Voltage-Max (Vsup) 5.5 V 3.6 V
Supply Voltage-Min (Vsup) 4.5 V 3 V
Supply Voltage-Nom (Vsup) 5 V 3.3 V
Surface Mount YES YES
Technology CMOS CMOS
Temperature Grade COMMERCIAL COMMERCIAL
Terminal Finish TIN LEAD
Terminal Form J BEND J BEND
Terminal Pitch 1.27 mm
Terminal Position QUAD QUAD
Base Number Matches 1 2
Package Description ,
ECCN Code EAR99
HTS Code 8542.32.00.71

Compare DS2012R-65 with alternatives

Compare CLS1-67204L-55 with alternatives