CY7C342-35GI vs CY7C342B-12RC feature comparison

CY7C342-35GI Cypress Semiconductor

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CY7C342B-12RC Cypress Semiconductor

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Rohs Code No No
Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer CYPRESS SEMICONDUCTOR CORP CYPRESS SEMICONDUCTOR CORP
Part Package Code PGA PGA
Package Description CAVITY-DOWN, CERAMIC, PGA-68 WINDOWED, CERAMIC, PGA-68
Pin Count 68 68
Reach Compliance Code not_compliant not_compliant
HTS Code 8542.39.00.01 8542.39.00.01
Additional Feature LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Clock Frequency-Max 22.2 MHz 62.5 MHz
In-System Programmable NO NO
JESD-30 Code S-CPGA-P68 S-CPGA-P68
JESD-609 Code e0 e0
JTAG BST NO NO
Length 27.94 mm 27.9527 mm
Number of Dedicated Inputs 7 7
Number of I/O Lines 52 52
Number of Macro Cells 128 128
Number of Terminals 68 68
Operating Temperature-Max 85 °C 70 °C
Operating Temperature-Min -40 °C
Organization 7 DEDICATED INPUTS, 52 I/O 7 DEDICATED INPUTS, 52 I/O
Output Function MACROCELL MACROCELL
Package Body Material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
Package Code PGA WPGA
Package Equivalence Code PGA68,11X11 PGA68,11X11
Package Shape SQUARE SQUARE
Package Style GRID ARRAY GRID ARRAY, WINDOW
Programmable Logic Type OT PLD UV PLD
Propagation Delay 75 ns 26 ns
Qualification Status Not Qualified Not Qualified
Seated Height-Max 2.667 mm 5.08 mm
Supply Voltage-Max 5.5 V 5.25 V
Supply Voltage-Min 4.5 V 4.75 V
Supply Voltage-Nom 5 V 5 V
Surface Mount NO NO
Technology CMOS CMOS
Temperature Grade INDUSTRIAL COMMERCIAL
Terminal Finish TIN LEAD TIN LEAD
Terminal Form PIN/PEG PIN/PEG
Terminal Pitch 2.54 mm 2.54 mm
Terminal Position PERPENDICULAR PERPENDICULAR
Width 27.94 mm 27.9527 mm
Base Number Matches 1 1

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