74LVT16652ADL-T
vs
74LVT16652ADL-T
feature comparison
All Stats
Differences Only
Rohs Code
Part Life Cycle Code
Obsolete
Transferred
Ihs Manufacturer
NEXPERIA
NXP SEMICONDUCTORS
Package Description
SSOP,
SSOP,
Reach Compliance Code
compliant
unknown
HTS Code
8542.39.00.01
8542.39.00.01
Date Of Intro
2017-02-01
Additional Feature
WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
Family
LVT
LVT
JESD-30 Code
R-PDSO-G56
R-PDSO-G56
Length
18.425 mm
18.425 mm
Logic IC Type
REGISTERED BUS TRANSCEIVER
REGISTERED BUS TRANSCEIVER
Number of Bits
8
8
Number of Functions
2
2
Number of Ports
2
2
Number of Terminals
56
56
Operating Temperature-Max
85 °C
85 °C
Operating Temperature-Min
-40 °C
-40 °C
Output Characteristics
3-STATE
3-STATE
Output Polarity
TRUE
TRUE
Package Body Material
PLASTIC/EPOXY
PLASTIC/EPOXY
Package Code
SSOP
SSOP
Package Shape
RECTANGULAR
RECTANGULAR
Package Style
SMALL OUTLINE, SHRINK PITCH
SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Cel)
NOT SPECIFIED
NOT SPECIFIED
Propagation Delay (tpd)
4.7 ns
4.7 ns
Seated Height-Max
2.8 mm
2.8 mm
Supply Voltage-Max (Vsup)
3.6 V
3.6 V
Supply Voltage-Min (Vsup)
2.7 V
2.7 V
Supply Voltage-Nom (Vsup)
3.3 V
3.3 V
Surface Mount
YES
YES
Technology
BICMOS
BICMOS
Temperature Grade
INDUSTRIAL
INDUSTRIAL
Terminal Form
GULL WING
GULL WING
Terminal Pitch
0.635 mm
0.635 mm
Terminal Position
DUAL
DUAL
Time@Peak Reflow Temperature-Max (s)
NOT SPECIFIED
NOT SPECIFIED
Width
7.5 mm
7.5 mm
Base Number Matches
1
1
Part Package Code
SSOP
Pin Count
56
JESD-609 Code
e4
Qualification Status
Not Qualified
Terminal Finish
Nickel/Palladium/Gold (Ni/Pd/Au)
Compare 74LVT16652ADL-T with alternatives
Compare 74LVT16652ADL-T with alternatives