74LVT16652ADGG-T
vs
74LVTH16652MTDX
feature comparison
| Rohs Code |
Yes
|
Yes
|
| Part Life Cycle Code |
Obsolete
|
Obsolete
|
| Ihs Manufacturer |
NEXPERIA
|
FAIRCHILD SEMICONDUCTOR CORP
|
| Package Description |
TSSOP,
|
6.10 MM, MO-153, TSSOP-56
|
| Reach Compliance Code |
compliant
|
unknown
|
| HTS Code |
8542.39.00.01
|
8542.39.00.01
|
| Date Of Intro |
2017-02-01
|
|
| Additional Feature |
WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
|
WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
|
| Family |
LVT
|
LVT
|
| JESD-30 Code |
R-PDSO-G56
|
R-PDSO-G56
|
| Length |
14 mm
|
14 mm
|
| Logic IC Type |
REGISTERED BUS TRANSCEIVER
|
REGISTERED BUS TRANSCEIVER
|
| Number of Bits |
8
|
8
|
| Number of Functions |
2
|
2
|
| Number of Ports |
2
|
2
|
| Number of Terminals |
56
|
56
|
| Operating Temperature-Max |
85 °C
|
85 °C
|
| Operating Temperature-Min |
-40 °C
|
-40 °C
|
| Output Characteristics |
3-STATE
|
3-STATE
|
| Output Polarity |
TRUE
|
TRUE
|
| Package Body Material |
PLASTIC/EPOXY
|
PLASTIC/EPOXY
|
| Package Code |
TSSOP
|
TSSOP
|
| Package Shape |
RECTANGULAR
|
RECTANGULAR
|
| Package Style |
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
|
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
|
| Peak Reflow Temperature (Cel) |
NOT SPECIFIED
|
|
| Propagation Delay (tpd) |
4.7 ns
|
5.6 ns
|
| Seated Height-Max |
1.2 mm
|
1.2 mm
|
| Supply Voltage-Max (Vsup) |
3.6 V
|
3.6 V
|
| Supply Voltage-Min (Vsup) |
2.7 V
|
2.7 V
|
| Supply Voltage-Nom (Vsup) |
3.3 V
|
3.3 V
|
| Surface Mount |
YES
|
YES
|
| Technology |
BICMOS
|
BICMOS
|
| Temperature Grade |
INDUSTRIAL
|
INDUSTRIAL
|
| Terminal Form |
GULL WING
|
GULL WING
|
| Terminal Pitch |
0.5 mm
|
0.5 mm
|
| Terminal Position |
DUAL
|
DUAL
|
| Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED
|
|
| Width |
6.1 mm
|
6.1 mm
|
| Base Number Matches |
1
|
2
|
| Part Package Code |
|
TSSOP
|
| Pin Count |
|
56
|
| Control Type |
|
INDEPENDENT CONTROL
|
| Count Direction |
|
BIDIRECTIONAL
|
| JESD-609 Code |
|
e3
|
| Max I(ol) |
|
0.064 A
|
| Moisture Sensitivity Level |
|
2
|
| Package Equivalence Code |
|
TSSOP56,.3,20
|
| Packing Method |
|
TR
|
| Power Supply Current-Max (ICC) |
|
5 mA
|
| Prop. Delay@Nom-Sup |
|
4.2 ns
|
| Qualification Status |
|
Not Qualified
|
| Terminal Finish |
|
MATTE TIN
|
| Trigger Type |
|
POSITIVE EDGE
|
|
|
|
Compare 74LVT16652ADGG-T with alternatives
Compare 74LVTH16652MTDX with alternatives