74LVC16240ADGG,518
vs
74LCXZ16240MTDX
feature comparison
| Rohs Code |
Yes
|
|
| Part Life Cycle Code |
Obsolete
|
Obsolete
|
| Ihs Manufacturer |
NXP SEMICONDUCTORS
|
FAIRCHILD SEMICONDUCTOR CORP
|
| Part Package Code |
TSSOP
|
TSSOP
|
| Package Description |
TSSOP, TSSOP48,.3,20
|
TSSOP, TSSOP48,.3,20
|
| Pin Count |
48
|
48
|
| Manufacturer Package Code |
SOT362-1
|
|
| Reach Compliance Code |
unknown
|
unknown
|
| HTS Code |
8542.39.00.01
|
8542.39.00.01
|
| Control Type |
ENABLE LOW
|
ENABLE LOW
|
| Family |
LVC/LCX/Z
|
LVC/LCX/Z
|
| JESD-30 Code |
R-PDSO-G48
|
R-PDSO-G48
|
| JESD-609 Code |
e4
|
|
| Length |
12.5 mm
|
12.5 mm
|
| Logic IC Type |
BUS DRIVER
|
BUS DRIVER
|
| Moisture Sensitivity Level |
1
|
|
| Number of Functions |
4
|
4
|
| Number of Ports |
2
|
2
|
| Number of Terminals |
48
|
48
|
| Operating Temperature-Max |
125 °C
|
85 °C
|
| Operating Temperature-Min |
-40 °C
|
-40 °C
|
| Output Characteristics |
3-STATE
|
3-STATE
|
| Output Polarity |
INVERTED
|
INVERTED
|
| Package Body Material |
PLASTIC/EPOXY
|
PLASTIC/EPOXY
|
| Package Code |
TSSOP
|
TSSOP
|
| Package Equivalence Code |
TSSOP48,.3,20
|
TSSOP48,.3,20
|
| Package Shape |
RECTANGULAR
|
RECTANGULAR
|
| Package Style |
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
|
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
|
| Peak Reflow Temperature (Cel) |
260
|
|
| Propagation Delay (tpd) |
6.5 ns
|
5.3 ns
|
| Qualification Status |
Not Qualified
|
Not Qualified
|
| Seated Height-Max |
1.2 mm
|
1.2 mm
|
| Supply Voltage-Max (Vsup) |
3.6 V
|
3.6 V
|
| Supply Voltage-Min (Vsup) |
1.2 V
|
2.7 V
|
| Supply Voltage-Nom (Vsup) |
3.3 V
|
3.3 V
|
| Surface Mount |
YES
|
YES
|
| Technology |
CMOS
|
CMOS
|
| Temperature Grade |
AUTOMOTIVE
|
INDUSTRIAL
|
| Terminal Finish |
Nickel/Palladium/Gold (Ni/Pd/Au)
|
|
| Terminal Form |
GULL WING
|
GULL WING
|
| Terminal Pitch |
0.5 mm
|
0.5 mm
|
| Terminal Position |
DUAL
|
DUAL
|
| Time@Peak Reflow Temperature-Max (s) |
30
|
|
| Width |
6.1 mm
|
6.1 mm
|
| Base Number Matches |
2
|
2
|
| Additional Feature |
|
5V TOLERANT INPUTS AND OUTPUTS
|
| Load Capacitance (CL) |
|
50 pF
|
| Max I(ol) |
|
0.024 A
|
| Number of Bits |
|
4
|
| Packing Method |
|
TR
|
| Prop. Delay@Nom-Sup |
|
4.5 ns
|
|
|
|
Compare 74LVC16240ADGG,518 with alternatives
Compare 74LCXZ16240MTDX with alternatives