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74LV00PW,112 vs 74LV00PW,698 feature comparison

74LV00PW,112 NXP Semiconductors

Buy Now Datasheet

74LV00PW,698 Nexperia

Buy Now Datasheet
Rohs Code Yes
Part Life Cycle Code Transferred Active
Ihs Manufacturer NXP SEMICONDUCTORS
Part Package Code TSSOP TSSOP
Package Description 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14
Pin Count 14 14
Manufacturer Package Code SOT402-1 SOT402-1
Reach Compliance Code compliant
HTS Code 8542.39.00.01
Factory Lead Time 4 Weeks
Family LV/LV-A/LVX/H
JESD-30 Code R-PDSO-G14
JESD-609 Code e4
Length 5 mm
Load Capacitance (CL) 50 pF
Logic IC Type NAND GATE
Max I(ol) 0.006 A
Moisture Sensitivity Level 1
Number of Functions 4
Number of Inputs 2
Number of Terminals 14
Operating Temperature-Max 125 °C
Operating Temperature-Min -40 °C
Package Body Material PLASTIC/EPOXY
Package Code TSSOP
Package Equivalence Code TSSOP14,.25
Package Shape RECTANGULAR
Package Style SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Packing Method TUBE
Peak Reflow Temperature (Cel) 260
Prop. Delay@Nom-Sup 18 ns
Propagation Delay (tpd) 31 ns
Qualification Status Not Qualified
Schmitt Trigger NO
Seated Height-Max 1.1 mm
Supply Voltage-Max (Vsup) 5.5 V
Supply Voltage-Min (Vsup) 1 V
Supply Voltage-Nom (Vsup) 3.3 V
Surface Mount YES
Technology CMOS
Temperature Grade AUTOMOTIVE
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal Form GULL WING
Terminal Pitch 0.65 mm
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) 30
Width 4.4 mm
Base Number Matches 2 2
Samacsys Manufacturer Nexperia
Logic » Gates
Logic » Gates

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