74ACTQ543QSC
vs
74ACTQ541PC
feature comparison
All Stats
Differences Only
Part Life Cycle Code
Transferred
Transferred
Ihs Manufacturer
NATIONAL SEMICONDUCTOR CORP
NATIONAL SEMICONDUCTOR CORP
Package Description
0.150 INCH, PLASTIC, QSOP-24
DIP, DIP20,.3
Reach Compliance Code
unknown
unknown
Additional Feature
MASTER CONTROL FOR LATCH AND OUTPUT ENABLES IN EACH DIRECTION
WITH DUAL OUTPUT ENABLE; MAX VOLP = 1.5V AT VCC = 5V, TA = 25 DEGREE C; MAX OUTPUT SKEW = 1000PS
Family
ACT
ACT
JESD-30 Code
R-PDSO-G24
R-PDIP-T20
Length
8.65 mm
24.892 mm
Load Capacitance (CL)
50 pF
50 pF
Logic IC Type
REGISTERED BUS TRANSCEIVER
BUS DRIVER
Number of Bits
8
8
Number of Functions
1
1
Number of Ports
2
2
Number of Terminals
24
20
Operating Temperature-Max
85 °C
85 °C
Operating Temperature-Min
-40 °C
-40 °C
Output Characteristics
3-STATE
3-STATE
Output Polarity
TRUE
TRUE
Package Body Material
PLASTIC/EPOXY
PLASTIC/EPOXY
Package Code
SSOP
DIP
Package Shape
RECTANGULAR
RECTANGULAR
Package Style
SMALL OUTLINE, SHRINK PITCH
IN-LINE
Propagation Delay (tpd)
9 ns
7.5 ns
Qualification Status
Not Qualified
Not Qualified
Seated Height-Max
1.75 mm
5.08 mm
Supply Voltage-Max (Vsup)
5.5 V
5.5 V
Supply Voltage-Min (Vsup)
4.5 V
4.5 V
Supply Voltage-Nom (Vsup)
5 V
5 V
Surface Mount
YES
NO
Technology
CMOS
CMOS
Temperature Grade
INDUSTRIAL
INDUSTRIAL
Terminal Form
GULL WING
THROUGH-HOLE
Terminal Pitch
0.635 mm
2.54 mm
Terminal Position
DUAL
DUAL
Width
3.9116 mm
7.62 mm
Base Number Matches
4
4
Part Package Code
DIP
Pin Count
20
HTS Code
8542.39.00.01
Control Type
ENABLE LOW
JESD-609 Code
e0
Max I(ol)
0.024 A
Package Equivalence Code
DIP20,.3
Prop. Delay@Nom-Sup
7.5 ns
Terminal Finish
Tin/Lead (Sn/Pb)
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