7142LA100JGB
vs
7142LA100L48BG
feature comparison
All Stats
Differences Only
Pbfree Code
Rohs Code
Part Life Cycle Code
Transferred
Obsolete
Ihs Manufacturer
INTEGRATED DEVICE TECHNOLOGY INC
INTEGRATED DEVICE TECHNOLOGY INC
Part Package Code
LCC
LCC
Package Description
QCCN, LDCC52,.8SQ
QCCN,
Pin Count
52
48
Reach Compliance Code
compliant
compliant
ECCN Code
3A001.A.2.C
3A001.A.2.C
HTS Code
8542.32.00.41
8542.32.00.41
Access Time-Max
100 ns
100 ns
Additional Feature
AUTOMATIC POWER DOWN
AUTOMATIC POWER-DOWN; BATTERY BACKUP
I/O Type
COMMON
JESD-30 Code
S-PQCC-N52
S-CQCC-N48
JESD-609 Code
e3
e3
Length
19.1262 mm
14.3002 mm
Memory Density
16384 bit
16384 bit
Memory IC Type
MULTI-PORT SRAM
MULTI-PORT SRAM
Memory Width
8
8
Moisture Sensitivity Level
1
Number of Functions
1
1
Number of Ports
2
Number of Terminals
52
48
Number of Words
2048 words
2048 words
Number of Words Code
2000
2000
Operating Mode
ASYNCHRONOUS
ASYNCHRONOUS
Operating Temperature-Max
125 °C
125 °C
Operating Temperature-Min
-55 °C
-55 °C
Organization
2KX8
2KX8
Output Characteristics
3-STATE
Package Body Material
PLASTIC/EPOXY
CERAMIC, METAL-SEALED COFIRED
Package Code
QCCN
QCCN
Package Equivalence Code
LDCC52,.8SQ
Package Shape
SQUARE
SQUARE
Package Style
CHIP CARRIER
CHIP CARRIER
Parallel/Serial
PARALLEL
PARALLEL
Peak Reflow Temperature (Cel)
260
Qualification Status
Not Qualified
Not Qualified
Screening Level
MIL-PRF-38535
MIL-PRF-38535
Seated Height-Max
4.572 mm
3.048 mm
Standby Current-Max
0.004 A
Standby Voltage-Min
2 V
Supply Current-Max
0.14 mA
Supply Voltage-Max (Vsup)
5.5 V
5.5 V
Supply Voltage-Min (Vsup)
4.5 V
4.5 V
Supply Voltage-Nom (Vsup)
5 V
5 V
Surface Mount
YES
YES
Technology
CMOS
CMOS
Temperature Grade
MILITARY
MILITARY
Terminal Finish
Matte Tin (Sn) - annealed
MATTE TIN
Terminal Form
NO LEAD
NO LEAD
Terminal Pitch
1.27 mm
1.016 mm
Terminal Position
QUAD
QUAD
Time@Peak Reflow Temperature-Max (s)
30
Width
19.1262 mm
14.3002 mm
Base Number Matches
3
2
Compare 7142LA100JGB with alternatives
Compare 7142LA100L48BG with alternatives