5962-8984105LC
vs
5962-8984105LA
feature comparison
| Part Life Cycle Code |
Obsolete
|
Obsolete
|
| Ihs Manufacturer |
CYPRESS SEMICONDUCTOR CORP
|
NXP SEMICONDUCTORS
|
| Package Description |
DIP,
|
DIP,
|
| Reach Compliance Code |
unknown
|
unknown
|
| ECCN Code |
3A001.A.2.C
|
3A001.A.2.C
|
| HTS Code |
8542.39.00.01
|
8542.39.00.01
|
| Additional Feature |
10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS
|
|
| Clock Frequency-Max |
83 MHz
|
42 MHz
|
| JESD-30 Code |
R-GDIP-T24
|
R-GDIP-T24
|
| JESD-609 Code |
e4
|
e0
|
| Length |
32 mm
|
|
| Number of Dedicated Inputs |
11
|
11
|
| Number of I/O Lines |
10
|
10
|
| Number of Terminals |
24
|
24
|
| Operating Temperature-Max |
125 °C
|
125 °C
|
| Operating Temperature-Min |
-55 °C
|
-55 °C
|
| Organization |
11 DEDICATED INPUTS, 10 I/O
|
11 DEDICATED INPUTS, 10 I/O
|
| Output Function |
MACROCELL
|
MACROCELL
|
| Package Body Material |
CERAMIC, GLASS-SEALED
|
CERAMIC, GLASS-SEALED
|
| Package Code |
DIP
|
DIP
|
| Package Shape |
RECTANGULAR
|
RECTANGULAR
|
| Package Style |
IN-LINE
|
IN-LINE
|
| Programmable Logic Type |
FLASH PLD
|
EE PLD
|
| Propagation Delay |
10 ns
|
15 ns
|
| Qualification Status |
Not Qualified
|
Not Qualified
|
| Seated Height-Max |
5.08 mm
|
5.08 mm
|
| Supply Voltage-Max |
5.5 V
|
5.5 V
|
| Supply Voltage-Min |
4.5 V
|
4.5 V
|
| Supply Voltage-Nom |
5 V
|
5 V
|
| Surface Mount |
NO
|
NO
|
| Technology |
CMOS
|
CMOS
|
| Temperature Grade |
MILITARY
|
MILITARY
|
| Terminal Finish |
GOLD
|
TIN LEAD
|
| Terminal Form |
THROUGH-HOLE
|
THROUGH-HOLE
|
| Terminal Pitch |
2.54 mm
|
2.54 mm
|
| Terminal Position |
DUAL
|
DUAL
|
| Width |
7.62 mm
|
7.62 mm
|
| Base Number Matches |
4
|
9
|
| Part Package Code |
|
DIP
|
| Pin Count |
|
24
|
| Package Equivalence Code |
|
DIP24,.3
|
| Screening Level |
|
MIL-STD-883
|
|
|
|
Compare 5962-8984105LC with alternatives
Compare 5962-8984105LA with alternatives